The present invention relates to semiconductor devices, and more particularly to methods of programming memory devices and memory devices.
Semiconductor memory devices may be typically classified into non-volatile memory devices that maintain stored data even though power is off and volatile memory devices that lose stored data when power is off. The non-volatile memory devices may include electrically erasable programmable read-only memory (EEPROM) in which stored data can be electrically erased and then new data can be reprogrammed.
Operations of an EEPROM may include a program mode for writing data into a memory cell, a read mode for reading the data stored in the memory cell, and an erase mode for initializing a memory cell by deleting the stored data. In an incremental step pulse programming (ISPP) method, verification and reprogramming may be repealed by using incremental step pulses until desired data is stored.
In flash memory devices pertaining to EEPROM, an erasing operation may be performed per memory block or sector, and a programming operation may be performed per page that includes a plurality of memory cells commonly coupled to a word line. The flash memory devices may be classified, according to a configuration of a memory cell array, into NAND Hash memory devices in which cell transistors may be coupled in parallel between a bitline and a ground electrode, and NOR flash memory devices in which cell transistors may be coupled serially between a bitline and a ground electrode. A NAND flash memory device may have higher programming and erasing speeds than a NOR flash memory device, but may not provide access per byte in reading and programming operations.
FIG. 1 is a timing diagram illustrating a conventional method of programming in a non-volatile memory device. Referring to FIG. 1, a power supply voltage Vcc is applied to an even bitline BLe and an odd bitline BLo at time t1. A voltage Vcc+Vth corresponding to a sum of the power supply voltage Vcc and a threshold voltage Vth of a string selection transistor is applied to a string selection line SSL at time t2. Thus, the string selection transistor is turned on and a channel of a memory cell is precharged at the power supply voltage Vcc.
When a program voltage Vpgm is applied to a selected wordline and a pass voltage Vpass is applied to unselected wordlines at time t3, the channel of the program-inhibited cell may be boosted to a voltage V1 higher than the power supply voltage Vcc due to capacitive coupling between the memory cells. When the program voltage Vpgm is deactivated at time t5, a cycle of a programming operation is finished.
FIG. 1 illustrates an example where the power supply voltage Vcc as a program-inhibiting voltage is applied to the program-inhibited bitline and the channel of the memory cell coupled to the program-inhibited bitline is boosted to the voltage V1 higher than the power supply voltage Vcc. On the contrary, a program-enabling voltage as a program-enabling voltage (for example, a ground voltage of 0 V) may be applied to a program-enabled bitline. The memory cell coupled to the program-enabled bitline can be programmed through Fowler-Nordheim (F-N) tunneling since a voltage difference between a floating gate and a channel may be relatively high in the memory cell coupled to the program-enabled bitline.
FIG. 2 is a diagram illustrating voltage variations of bitlines and channels in the programming method of FIG. 1. The voltage variations according to ISPP, in which voltage levels of pulses are sequentially increased by a step ΔISPP, are illustrated in FIG. 2 with respect to a program-inhibited even bitline BLe, a channel of a memory cell coupled to the program-inhibited even bitline BLe, a program-inhibited odd bitline BLo, and a channel of a memory cell coupled to the program-inhibited odd bitline BLe.
A precharge voltage (for example, a power supply voltage Vcc) may be simultaneously applied to the bitlines BLe and BLo before (N−2)th through (N+2)th pulses are sequentially applied to a selected wordline. Thus, program-inhibited even and odd bitlines BLe and BLo may be maintained at the power supply voltage Vcc and the channels of the memory cells coupled thereto may be boosted to a voltage V1 higher than the power supply voltage Vcc when the pulse is applied to the selected wordline.
For example, the even bitlines BLe can be selected so that the memory cells coupled to the even bitlines are programmed according to loaded program data. In this case, the voltages of the even bitlines BLe may become either the power supply voltage Vcc (i.e., the program-inhibiting voltage) or the ground voltage of 0 V (i.e., the program-enabling voltage) according to each bit of the loaded program data. For convenience of description. the voltage of the program-enabled even bitlines is omitted in FIG. 2. The unselected odd bitlines BLo maintain the program-inhibiting voltage, that is, the power supply voltages Vcc regardless of the bit values of the program data, which are loaded, for example, in page buffers.
As the integration degree of a memory device is increased and the size of memory cells therein is decreased, a capacitance between a channel and a floating gale may be increased and a leakage current from the channel to a substrate body may be increased. The increased capacitance and the leakage current cause program disturbance since the boosted voltage V1 of the channel is decreased. The program disturbance represents undesired programming such that the memory cells coupled to the program-inhibited bitlines are programmed because the voltage difference between the channel and the floating gate is great enough to induce the F-N tunneling due to an insufficient boosting effect.
In a non-volatile memory device using a relatively low power supply-voltage as a precharge voltage, the program disturbance may become more serious. The higher power supply may be required to reduce the program disturbance. A method of increasing a boosting efficiency is disclosed in Japanese Patent Laid-Open Publication No. 1999-120779, capable of obtaining a higher channel voltage by increasing a boosting efficiency with the same level of a power supply voltage.
FIG. 3 is a circuit diagram illustrating a conventional non-volatile memory device. Referring to FIG. 3, the non-volatile memory device includes a memory cell array 10 consisting of memory cells 11 coupled to even bitlines BLe and memory cells 12 coupled to odd bitlines BLo. A pair of even and odd bitlines is commonly coupled to each page buffer 20 through bitline selection transistors T11 and T12.
The switching operation of the bitline selection transistors T11 and T12 is controlled by selection signals SS1 and SS2. The bitlines BLe and BLo are coupled to transistors T21 and T22 for applying precharge voltages VA1 and VA2 (for example, a power supply voltage Vcc), respectively, and the transistors T21 and T22 are controlled by precharge signals PRA1 and PRA2.
In the non-volatile memory device 50, the precharged bitlines BLe and BLo may be boosted by controlling activation timings of the precharge signals PRA1 and PRA2, and then the bitline selection transistors may be simultaneously turned on. Accordingly, the even and odd bitlines BLe and BLo commonly have a boosted voltage Vbst by charge sharing after the precharge operation is completed. The boosted voltage may be determined in Equation 1, as follows:Vbst=(Vcc+βVcc)/2=(1+β/2)Vcc  Equation 1
where a power supply voltage Vcc is used as a precharge voltage, and a bitline coupling coefficient β is determined according to a configuration of the memory cell formed in the substrate.
FIG. 4 is a diagram illustrating voltage variations of bitlines and channels in the non-volatile memory device of FIG. 3. Since the bitline coupling coefficient β is a positive value, the bitlines are boosted to a voltage (1+β/2)Vcc that is greater than the precharge voltage Vcc and the channels of the memory cells coupled to the program-inhibited even and odd bitlines BLe and BLo are commonly boosted to a voltage V1a. The boosted channel voltage V1a of FIG. 4 is greater than the boosted channel voltage V1 of FIG. 2.
The non-volatile memory device 50 can increase a channel voltage by capacitive coupling between the adjacent bitlines. A time for turning on the transistors T11 and T12, however, may be required for the charge sharing between the adjacent even and odd bitlines BLe and BLo, and thus the programming time may be increased. If the incremental step pulses are used as the program voltage Vpgm, increased turning-on time of the transistors T11 and T12 may be required for each step pulse and the entire programming time may be further increased.